SSB and CW Transceiver


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My current (2010) software defined radio (SDR) project is an SSB and CW receiver and exciter on the same board.  It is the successor to my SSB exciter from 2007.  It improves on the 2007 hardware by using a 10/100 Ethernet controller, eliminating the microcontroller bottleneck, and including a receiver on the same board.  You should still read my 2008 QEX article for background.

The hardware design is very straight forward.  A block diagram is available here.  In the center is an Altera FPGA and its program storage chip.  This is connected to everything else:
The major parts were all purchased from Digikey and are a follows:
A few people have expressed interest, so I am providing the design files as an open source project.  Please note that THERE ARE NO WARRANTIES.   I have a full time job, and can supply only a little support to interested parties.

If you want to play with software defined radio and need a place to start, feel free to study or build this project.  I suggest you mount just the FPGA first, and test it with the usual LED blink program.  Then mount the Ethernet controller and test it with Ping.  Then you can mount the more expensive ADC or DAC or both.

This project is just a transceiver.  To make a complete station you need amplifiers and filters.  A block diagram and description of the rest of my station is here.

Photos

Here is a screenshot of Quisk running with the new hardware.  It shows the whole 40 meter amateur band sampled at 480000 samples per second.  Here is a photo of the hardware and a photo of the PC board.

PC Board

The PC board design is "finished" and was done with Eagle.  The design files as of December 2009 are in eagleboard.zip.  This is a rev 2 board and there are some problems you may want to fix if you are going to make more boards.

The board is two-layer because multi-layer boards are very expensive in quantity one.  But this creates problems with noise.  To reduce noise, I left as much copper as possible on both sides.  As a result, there are a number of jumpers that must be added.  The board should really have at least four layers.

The remaining problems are:
The input power is 6.0 volts, and I mounted TO-220 regulators on the chassis for 5.0, 3.3 and 1.2 volts.  The 2.5 volt regulator is on the board.

I built the DAC low pass filter and preamp on the board using "ugly" construction (there are no board traces).  The alternative is to run the DAC output directly to the BNC.  The board has a lot of empty space for this type of modification.

Software

The transceiver is controlled by my Quisk software.  If you do not want to use Quisk, just attach your own software.  Audio samples from the receiver are pairs of 24-bit I/Q samples starting at UDP data position 2 (Ethernet position 44).  The first byte of UDP data is a sequence number that you can ignore, or use to check for errors.  The second status byte carries the key /up/down state and an ADC overrange bit.  To transmit, send two 8-bit zeros followed by 16-bit I/Q audio samples to UDP port 0xBC79 at a 48 kHz rate.  For control, check the simple UDP code in quisk_hardware_n2adr.py.

The FPGA software is written in Verilog for the Altera free Web Edition development environment.  You will need a programming cable to connect the 2X5 header to your PC.  I use the Terasic P0302 USB cable (Digikey P0302-ND) instead of the more expensive Altera cable.

The FPGA project files are now final (or as final as homebrew projects ever get), and a here is the latest version from April 2010.  The decimation from the 122.880 megahertz clock is 8 times the decimation specified in the config file (2 to 40) times 8.  That results in a final sample rate of 48000 to 960000 samples per second.  At 960000 sps and 48-bit samples, the Ethernet bandwidth is 46 megabits per second plus 1.5 mbs for transmit plus overhead, or about half the available 100 mbs Ethernet bandwidth.

Status

2010 May:  The hardware and software are finished and work well.  I submitted an article describing this project to QEX.

2010 April:  Thanks to an email from Jeff Millar, WA1HCO, I now understand the high noise figure.  He calculated the noise figure of the ADC alone to be 30 dB.  The preamp gain is not sufficient to dominate the noise figure, and using the usual formula F = F1 + (F2 - 1) / G1 gives the net noise figure I observe.  I do not want more preamp gain, as that would degrade the dynamic range.  I have an additional preamp external to the transceiver that I can switch in for 20 meters and up.

2010 April:  The FPGA software is almost finished.  I added the ability to specify the decimation rate in the Quisk config file.  SSB transmit and receive both work.

2010 January: The receiver noise figure is 24 dB.  Although this is not bad, the preamp noise is dominant, and I was expecting a noise figure closer to the preamp noise figure of 7.5 dB.  I do not understand why the noise figure is 24 dB.  The transmitter audio is good.  The output from a low pass filter connected to the DAC transformer is 2.2 dBm at 1.9 MHz, 1.6 dBm at 14.2 MHz, and 0.5 dBm at 30 MHz.  The 20 ma peak (10 ma after the transformer) from the DAC to parallel 180 and 50 ohm loads would give 1.85 dBm in the 50 ohm load.  This goes to a 2N5109 amp with 15 dB gain, but the IMD is about 35 dB below one tone.   At this power level, lower IMD is expected, so I plan to reduce the gain.

2010 January:  The FPGA software now generates both CW and SSB.  Two-tone output is generated in audio and sent as SSB, and looks good.

2009 December:  This project is not finished and currently is under development.  The board is done and all the parts are mounted.  Receive mostly seems to work, although the noise level is higher than it should be.  The transmitter generates sin waves but not SSB.